• Package Level Integration
Packages are stacked and interconnected using conventional wire bonds or flip chip processes to create traditional stacked die and stacked package structures, including:
Stacked Die (SD) packages which typically consist of bare die stacked and interconnected using wire bond and flip chip connections in one standard package. Configurations include FBGA-SD, FLGA-SD, PBGA-SD, QFP-SD and TSOP-SD.
Package-on-Package (PoP) packages which typically consist of stacking fully tested memory and logic packages eliminating known good die (KGD) issues and providing flexibility in mixing and matching IC technologies. Flip chip PoP options include Bare Die PoP, Molded Laser PoPand an exposed die Molded Laser PoP configuration (PoP-MLP-ED).
Package-in-Package (PiP) packages which typically stack packaged chips and bare chips into one JEDEC standard FBGA. A pre-tested Internal Stacking Module (ISM) Land Grid Array (LGA) and a BGA or a Known/Probed Good Die (KGD) are stacked and interconnected with wire bonding, then molded into a CSP that is indistinguishable from a conventional FBGA package.